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Parallel MAC unit based on modified booth algorithm [Help needed]


Guest gstekboy

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Guest gstekboy

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time.
aYJKo.jpg

The partial product summation + accumulation unit of above parallel mac is given below. (link to the image).

qIftF.jpg

My problem : When I give input to multiplier as 00000101(5) and 00001000( 8 ) what will be the values produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3 that can be used as input of partial product generation + accumulation stage.

The complete document is shared below.


Please share your ideas.I need to continue my project based on your replies.
Thanks.

parallel_mac_base.pdf

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