Capacitor Charging with HV Pulses

[Kerrowman]

I have some queries regarding capacitor charging using inductively generated HV pulses, in contrast to with regular DC. First, to check my understanding, I will recount the situation with non-pulsed DC.

If the energy supplied by the battery U = QV then the capacitor will always(?) receive and store 1/2 QV (= 1/2 CV^2) due to resistive, inductive and radiative losses.

So with a known value of capacitor being charged from a voltage V_min to V_max, as seen on a scope trace, one can calculate the energy stored and compare it to what was delivered by the battery and, at best, this will be 50%. In practice it will likely be less due to other losses.

If the capacitor is then discharged, whatever energy was stored will again incur resistive losses, (possibly up to 50%?) such that, over a complete cycle of charging and discharging, perhaps only 25% of the original energy supplied by the battery is available for whatever the discharge energy might be used for.

Looking now at the situation with HV pulses, of the sort produced from the field collapse of a coil (flyback pulses), then the situation may be quite different and I am seeking to understand how charging takes place and, more importantly, the losses incurred during the charging and discharging stages.

With reference to the diagram on the link below, the capacitor is made up of 4 x 15mF 80V low ESR caps connected in parallel and with a combined measured value of 53mF.

https://ibb.co/ZTLJNpR

The output pulses have a peak voltage of 1.7kV, a FWHM of 20us and a PRF of 50Hz and, on the face of it, the time-averaged voltage across the capacitor is zero since after the pulse rise time to a peak voltage it returns again to zero before the next pulse. However, practical measurements show a very real and rapid rise in capacitor voltage using such pulses, so clearly the pulses are resulting in a positive charge and voltage differential across the capacitor plates.

What I presume is happening is that with each HV pulse the capacitor starts to charge a little and, when the pulse voltage returns to zero, the capacitor is unable to discharge due to the presence of the top diode and the VDSwitch. As such the capacitor charges in small discrete steps in a staircase fashion and this is what appears as the ‘fuzzy’ charging curve on the 'capacitor voltage’ insert.

Assuming this is basically correct, of more interest is what losses are incurred in the charging and discharging stages and whether they are larger or smaller than with regular DC?

The reason for the interest is for my research into non-linear and ‘far from equilibrium’ effects of these voltage transients on batteries and capacitors. If the losses are such that, in a complete charge and discharge cycle, I am going to see more or less than approximately 25% of the battery input energy, then that is very significant.

Sorry for the long post but it’s important that I give a clear picture of the setup and context.

 

[HarryA]

I put that circuit into the LTspice circuit simulator but the simulator is not happy with it. I will try later to get it to work. The simulator would give insight into what the currents look like.

[Kerrowman]

Hi Harry,

I am reliably informed that the circuit I posted is pretty much the same as a Boost Converter (with my added VDS) where the transfer of energy on charging is close to 100% due to the way the energy is stored in the coil’s magnetic field before being transferred with high efficiency to the capacitor (with some very small resistive losses). That being so the remaining question is what % is lost when one discharges the capacitor into a regular load, such as another battery or an electronic load? Does it loose 50% precisely like conventional charging with DC or can it vary?

If you get the sim to work it will be interesting to see if it predicts or shows the same.

Incidentally, you gave me some help a couple of years back on various themes and you might be interested to see what it was leading to. My recently published paper will explain and I acknowledged you, amongst various others, in the replication manual.

https://doi.org/10.33140/JEEE.03.04.05

Julian

 

[HarryA]

The results from the LTspice simulation. Beware that sometimes the simulators lie.

In the first plots the the red line is the voltage across capacitor c1. The green line is the voltage at the mosfet drain. The voltages peaks at 1.34 kv in 24 seconds. The green plot is solid as it is maded up of pulses. The breaks in the red plot are do to the scaling in the Gimp image processing software.

In the next three plots; the white plot is the input to the mosfet. 6v peak, 50hz, 20ms high and 20 ms low. The red plot is the current from the mosfet; at 0.905 amperes. While the green plot is the current through one of the coils at 0.301 amperes.

Attach is the circuit as used in the simulation. Using components close to the original circuit that the simulator has.

 

 

[Kerrowman]

Hi Harry,

Thank you, that is very interesting. The VDS (a comparator and high-sided P-FET) is just a way to discharge the capacitor so it can repeat its charging and show multiple traces on the scope from which I can take measurements and do calculations.

Is it possible to determine the energy transferred to the capacitor from the voltage and current values indicated by the graphs?

What is even more important is for me to determine what energy is transferred during a discharge to a regular load. In the past I have done this using an electronic load (computerised battery analyser) and where I read off the Wh dissipated. This is shown in this image (also attached):

https://ibb.co/xGcTdrq

So if the losses in discharging like this are always precisely 50% then I can say that the energy the cap held before discharge was 62.1J / 0.5 = 124.2J. But if the resistive losses are not 50% then I would need to calculate it, maybe by first finding out the resistance value of the electronic load?

Julian

[Kerrowman]

Actually, I now understand that all the discharge energy will in fact be dissipated in the electronic load, so there is no 50% here.

So my question changes to: assuming the sim components are accurate, how can one use the sim data to derive the efficiency of the delivery of energy to the capacitor?

It should be relatively straightforward to measure and calculate the resistance from the coil to the capacitor, consisting of the coil’s resistance, Rds On for the FET and the resistance from the Drain to the capacitor.

Knowing the energy held in the capacitor from the discharge, together with the transfer efficiency, will give what was initially ‘sent’ to the capacitor. Assuming a 95% efficiency, for example, is not accurate enough for the data to test the hypothesis proposed for my 2nd study.

 

Harry, I have just noticed an error on your sim design. My capacitor is 53milliF not 53microF. That will change a few things. 😊

[Kerrowman]

Hi Harry,

 

I have obtained a fairly good Spice model now, as per the diagram, that works quite well. It is not especially accurate in calculating efficiency, since the model does not include skin effects and other parasitic inductance and capacitance values. I have attached some calculations using this.

 

My query now is, how would the resonance of the LCR circuit show in the sim circuit? By that, I mean what node measurements would I make, and any ensuing calculations, to show that at a certain frequency, resonance was occurring? I have done a nominal calculation on the diagram which suggests that resonance might occur at just over 2Hz, but it may be different when it comes to pulse charging, in contrast to DC or a sine wave.

 

Any thoughts would be appreciated.

 

Thanks

[HarryA]

I think you would find this free Power Electronics course from MIT very helpful. The math is not to bad 😉

I find it very interesting. There are 38 lectures in all; by the end you have a good understanding of power circuits.

 

Power Electronics

[Kerrowman]

Hi Harry,

I’m sure it’s very good and interesting but it deals with far more than I need to address linked to my research studies. I simply don’t have the time anyway with publication deadlines.

Is there no guidance you can offer on the specific question as to where I would probe the sim circuit to observe resonance?

J

[HarryA]

Try this. On your schematic window click on a blank area. Select Edit Simulation CMD then in the popup dialog box select AC Analysis. Select Linear or Decade(?) . Then I used: 500, 30k, 50k. Next click on the signal symbol and set then AC voltage to some value.  On running the simulation I got a peak at 39.36k.

Your schematic is further along then mine so you should get different results. I used the 53000u for the capacitor.

This guy uses a different approach but I can not follow him

Ltspice video

[Kerrowman]

Thanks for that. The video is also useful as I have the Mac version of Spice so can follow him fine. 😊

However, when I follow his steps I am not allowed more than one IC so when just using one, and the expression 'tran 0 1m', I get another error saying 'missing nodes'. I'm not sure how to proceed here. 

What is strange is that your graph shows a resonance at approaching 40kHz whereas my calculation comes up with around 2Hz. I guess the model doesn't match reality?

[HarryA]

I will message you a temp email address. You could  try  sending me an email with your  LTspice  .asc file as an attachment. I could play with it. If I can figure how to do messaging. 

[Kerrowman]

Sure, that's very kind of you. I will compress the .asc and the .mdl file together. Can I place the zip file on my G-Drive and post a link here? Will that get through?

Sending separate files to you.