IMAGO Technologies, a leading developer of industrial machine vision solutions, today unveiled the Vision Cam XM2, a powerful and compact smart camera powered by the NVIDIA Jetson Orin™ module. This revolutionary embedded vision system delivers unmatched performance and flexibility for edge AI applications and other tasks demanding multi-core ARM and GPU processing power.
The Vision Cam XM2 represents a paradigm shift in edge AI, empowering businesses to harness the power of complex computations directly on-camera, thanks to the NVIDIA Jetson Orin module. This eliminates the need for additional hardware, translating to efficient, cost-effective execution and seamless integration into existing systems, even in space-constrained environments.
Equipped with a high-resolution sensor, the Vision Cam XM2 captures up to 5 megapixels per image and 165 frames per second at full resolution, making it ideal for high-speed inspection and processing tasks where precision and speed are paramount. Even at VGA resolution, it can capture up to 1,400 frames per second. The camera can also be deployed as a line scan camera.
Beyond its performance, the Vision Cam XM2 boasts exceptional flexibility and programmability. It readily supports AI-based applications, intricate pattern recognition processes, and the combination of numerous operators, making it a versatile tool for developers of image procession systems. Additionally, unlike solutions reliant on short-lived GPUs, the Vision Cam XM2 guarantees long-term availability and integration in line with mechanical engineering standards, positioning it as a future-proof choice for industrial image processing.
The integrated processor, featuring 6x ARM Cortex A78 CPUs, 1024 GPU cores, and 32 Tensor cores, unleashes remarkable processing power, enabling real-time execution of even complex AI algorithms. This opens doors to innovative applications in automation and quality assurance, paving the way for a new era of industrial image processing potential.
IMAGO will be showcasing the capabilities of the Vision Cam XM2 live at Embedded World.
The Fourier Transform is a mathematical technique that transforms a time-domain signal into its frequency-domain representation. In other words, it decomposes a signal into its frequency components. The result is called the spectrum of the signal. Historically, the Fourier analysis concept developed slowly, from the Fourier series method 200 years ago up to the Discrete Fourier Transform (DFT) computing method today. Essentially, the Fourier decomposition was unsatisfyingly slow, often requiring several minutes to execute on present-day computers. The Fast Fourier Transform (FFT) is a family of algorithms developed in the 1960s to reduce this computation time.
The discovery of the Fast Fourier Transform (FFT) by J. W. Cooley and John Tukey in 1965, revolutionized signal processing. Cooley and Tukey are credited with introducing the FFT to the world in their paper: “An algorithm for the machine calculation of complex Fourier Series”, Mathematics Computation, Vol. 19, 1965, pp 297-301.
In practice, we often deal with discrete signals, which are represented as a sequence of samples taken at discrete time intervals; digital computers work with such signals. The discrete Fourier transform (DFT) applies to signals that are discrete in time and aperiodic. Based on the Fourier analysis theory, an aperiodic signal is composed of an infinite number of sines and cosines. The DFT is defined as the sum of the product of the signal values and complex sinusoidal functions (called basis functions) at different frequencies.
The direct computation of the DFT involves nested summations or recursive computations, making it computationally expensive. The O() notation is used to describe the worst-case scenario of the algorithm’s time complexity. It provides an asymptotic upper limit on how the running time increases as the input size (number of samples) grows. The time complexity of a direct DFT implementation is O(N2), where N is the number of discrete samples in the signal. This means, that in such a scenario in which the algorithm would involve nested loops, it results in a quadratic growth in running time as the input size (N) increases.
The FFT as an algorithmic technique made the computation of the Fourier transform simpler and quicker and finally allowed Fourier analysis to be recognized and used more widely. In this method, by eliminating duplicate computations in the DFT, it became possible to produce the frequency spectrum of a signal with N data points in (N.log2N) operations. This made real-time digital signal spectrum analysis feasible. Figure 1 shows a general example of the FFT operation on a small sequence with 8 samples.
Figure 1: A general diagram of the Fast Fourier Transform operation with N = 8 discrete data
The Fast Fourier transform has been widely used in the field of digital signal processing. Back in 1988, a 256-point FFT still consumed minutes of PC time. Today, an 8192-point FFT (8k FFT) takes less than one millisecond of computing time! This opens the door for new and interesting applications such as digital videoandaudio compression and test engineering or Orthogonal Frequency Division Multiplex (OFDM) in telecommunication systems. In modern storage oscilloscopes, the FFT makes it possible to perform a low-cost spectrum analysis. The FFT has also been used in the field of acoustics and geology.
Review Of Discrete Fourier Transform (DFT)
In the previous article, we considered the DFT method:
The forward complex discrete Fourier transform (DFT) of x, also known as the spectrum of x, is defined by Equation 1.
Equation 1: The forward DFT in exponential form
This is more commonly written as Equation 2.
Equation 2: The different notation for the forward DFT
and, WN for k = 0 … N−1, are called the Nth roots of unity. The sequence X[k] is the discrete Fourier transform of the sequence x[n]. Each is a sequence of N complex numbers which are composed of two numbers, the real part and the imaginary part. For example, the complex sample X[15], refers to the combination of Re X[15] and Im X[15]. Then, Equation 1 (or 2) saves a lot of additions and multiplications, as complex operations, not real.
However, the DFT can be solved by simple mathematical and numerical means and it functions both forwards and in the reverse direction in the time domain (Inverse Discrete Fourier Transform – IDFT). Similarly, Equation 3 describes the method of inverse calculation.
Equation 3: The different notation for the inverse DFT
The result of performing a DFT on a real-time domain signal interval is a discrete complex spectrum (real and imaginary parts). The IDFT transforms the complex spectrum back into a real-time domain signal again.
The Fast Fourier Transform (FFT)
The Discrete Fourier Transform is a simple but fairly time-consuming algorithm. However, if the number of points N within the window of observation is restricted to N = 2m, i.e. a power of two, a more complex but less time-consuming algorithm can be used, which is called the Fast Fourier Transform (FFT). This algorithm provides the same result as a DFT but is much faster and restricted to N = 2m points (2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, …).
It is important to clarify that the DFT and FFT are not completely different entities. The FFT is a collection of efficient algorithms for calculating the DFT with a significantly reduced number of computations. The Discrete Fourier Transform and the Fast Fourier Transform are all defined through the field of complex numbers. The Fast Fourier Transform can also be inverted (Inverse Fast Fourier Transform – IFFT). Figure 2 describes the FFT numerical structure.
Figure 2: The FFT data structure
The complex FFT transforms two N point time domain signals into two N point frequency domain signals. The two time-domain signals are called the real part and the imaginary part, just as are the frequency-domain signals. Despite their names, all of the values in these arrays are just ordinary numbers. (The j’s are not included in the array values! They are a part of the mathematics of complex numbers).
As the N samples of a typical time domain signal are always purely real, the corresponding imaginary part must be set to zero for each of the N points. This means that the imaginary-part table for the time domain must be filled with zeros.
Mechanism Of The FFT Operation
The FFT is an algorithmic approach to compute the DFT which exploits the symmetry and periodicity properties of sinusoidal functions to speed up the computations. The FFT makes use of methods of linear algebra. The samples are pre-sorted in co-called bit reversal and then processed using butterfly operations. These operations are implemented as machine codes in signal processors and/or special FFTchips.
Let’s review the method of the Fast Fourier Transform:
The FFT algorithm efficiently exploits the fact that for a power-of-2 size signal (N = 2m), the DFT can be expressed in terms of smaller DFTs.
The fundamental principle behind the FFT algorithms is to divide the computation of the DFT of N samples into successively smaller DFTs, recursively compute their solutions, and then combine these solutions to get the final DFT result.
The Cooley-Tukey algorithm is one of the most widely used FFT algorithms and the Radix-2 decimation-in-time (DIT) is the simplest and most common form of the Cooley–Tukey algorithm.
Decimation involves dividing the input sequence into smaller sub-sequences, which are then processed recursively to compute the FFT.
Radix-2 DIT divides a DFT of size N into two interleaved DFTs (hence the name “radix-2”) of size N/2 with each recursive stage.
The algorithm operates by decomposing an N point time domain signal into N time domain signals each composed of a single point. The second step is to calculate the N frequency spectra corresponding to these N time domain signals.
The Radix-2 FFT has a time complexity of O(N.log2N), which is a significant improvement over the O(N2) complexity of the direct DFT.
The first step of the Radix-2 decimation-in-time (DIT) procedure is the time domain decomposition of input samples. Figure 3 shows an example of decomposition used in the FFT for the case of N = 8. On the left, the indexes of the original signal samples are listed along with their binary equivalents. On the right, the rearranged sample numbers are listed similarly.
Figure 3: The bit reversal sorting algorithm for N= 8 samples
An interlaced decomposition is used each time a signal is broken in two, that is, the signal is separated into its even and odd sample indexes. Essentially, the decomposition is nothing more than a reordering of the samples in the signal.
The important idea is that the binary numbers are the reversals of each other. For example, sample number 3 (0112) is exchanged with sample number 6 (1102), and so forth. Some of the sample numbers also remained unchanged, like 0 and 7. Then, the FFT time domain decomposition is usually carried out by a bit reversal sorting algorithm. This involves rearranging the order of the N time domain samples by counting in binary with the bits flipped left for right. The data x[n] after decomposition is stored in bit-reversed order. Figure 3 shows the required rearrangement pattern.
Figure 4 shows the FFT butterfly. This is the basic calculation element in the FFT, taking two complex points and converting them into two other complex points by addition and multiplication operations. This simple flow diagram is called a butterfly due to its schematic shape.
Figure 4: (a) The FFT butterfly operation schematic diagram (b) The simplified diagram
This typical FFT butterfly operation involves two complex numbers as inputs, denoted as yk[0] and yk[1]. The operation transforms these two values into two new values, (yk[0] + Wk. yk[1]) and (yk[0] – Wk. yk[1]), following specific mathematical rules. We can call the results, for example, A and B. Then, the butterfly operation computes new values for sum and difference as described in Equation 4.
Equation 4: A mathematical description of the butterfly operation
In Equation 4, W is a complex root of unity. In the Cooley-Tukey Radix-2 FFT, W is a twiddle factor that depends on the size of the FFT and the stage of computation.
The butterfly operation is then repeated recursively in different stages of the FFT algorithm, ultimately leading to the efficient computation of the DFT. Understanding the butterfly operation is crucial for grasping the inner workings of the FFT algorithm, and it provides insight into how the FFT efficiently decomposes and combines frequency components during its computation.
Figure 5 shows the general idea behind the FFT algorithm and how to produce the N-point frequency spectra from the N-point time domain data.
Figure 5: The Block diagram of the FFT operation
Let’s go through an example of computing a 4-point FFT (N= 4) using the Cooley-Tukey Radix-2 FFT algorithm. For N= 4, the twiddle factor W is W4 = e−2πi/4 = e-πi/2.
Step-By-Step Calculation For N=4 FFT
Start The Algorithm
We start with the original input sequence with arbitrary values {x[0], x[1], x[2], x[3]} and we define samples with even and odd indexes.
Stage 1:
The FFT butterfly operations at this stage involve twiddle factor W4 raised to the power of 0.
Butterfly 1
In the first butterfly operation, we combine x[0] and x[2] as samples with even indexes.
x[0] and x[2] are added and subtracted, respectively, using the twiddle factor W0.
Butterfly 2
In the second butterfly operation, we combine x[1] and x[3] as samples with odd indexes.
x[1] and x[3] are added and subtracted, respectively, using the twiddle factor W0.
Stage 2:
Now, we perform the butterfly operations again using twiddle factor W4 raised to the power of 0 or 1.
Butterfly 1
We run another set of butterfly operations, combining the outputs from the previous stage.
The result of (x[0] + x[2]) is combined with (x[1] + x[3]), using the twiddle factor W0.
Butterfly 2
(x[0] – x[2]) are combined with (x[1] – x[3]) using W1.
The Final Result
The final sequence X which contains {X[0], X[1], X[2], X[3]}, is the Fourier Transform of the original sequence x. The method of computation is explained by Equation 5. The results are equal to the DFT results.
Equation 5: The set of equations of the FFT algorithm for the example N= 4
Visualization Of Butterfly Mechanism
Let’s visualize the butterfly mechanism for the FFT computation with N=4. In this case, we have two stages of computation. Each stage involves two butterfly operations. The procedure is plotted in Figure 6. The arrows represent the flow of data through the butterfly operations. Each butterfly operation combines two inputs and produces two outputs.
Figure 6: The block diagram of Radix-2 FFT algorithm for the case of N = 4
In the FFT computation process, the number of outputs is always equal to the number of inputs, and it matches the size of the input sequence. Therefore, for N=4, we have four input elements (x[0], x[1], x[2], x[3]) and four corresponding output elements (X[0], X[1], X[2], X[3]).
Example Calculation
We can consider a realistic example by calculating the FFT for the input sequence x = {1, 2, 3, 4}. Based on the above-mentioned Equation and using (W0 = 1) and (W1 = -j), we can find the solution as explained in Table 1.
Table 1: An example of FFT calculation with N =4
This simple example illustrates the basic steps of the FFT algorithm for N= 4. In practice, for signals with many more elements (N >> 4), the FFT algorithm efficiently performs the transformation of these operations using a recursive strategy, reducing the overall computational complexity.
Spectrum Of The Signal Based On FFT Calculations
To generate a frequency domain plot from this data, the magnitude and the phase of each complex sample must be calculated using Equations 6 and 7.
Equation 6: Calculation of the magnitude of spectral componentsEquation 7: Calculation of the phase of spectral components
The results of the calculation are summarized in Table 2.
Table 2: The example of FFT calculation with N = 4 in terms of magnitudes and phase angles
The results are then plotted in Figure 7. In the graph, the horizontal axis is the frequency in terms of sample indexes, and the vertical axis is the amplitude. A 0 frequency component indicates the amplitude of the DC component of a signal which is the sum of all the sample values in the sequence.
Figure 7: The FFT complex frequency spectrum with N = 4 in terms of the magnitude and the phase
Comparison Of Computational Complexities Between DFT And FFT Methods
If N samples are given to a DFT, the time it takes to compute the amplitudes of the sinusoids is proportional to N2. But, the Radix-2 FFT algorithm requires only N·log2N complex operations. For example, for a 1024-point transform, the DFT requires 1,048,576 complex operations compared to only 10,240 for the FFT.
Table 3 shows the speed improvement of the FFT over that of the DFT in terms of different values of N.
Table 3: Comparison between the computational speeds of the DFT and the FFT for various values of N
It is clear that the speed improvement is quite significant for larger values of N and this is the main efficiency of the FFT for real discrete signals with large sizes, like N = 1024 and so on.
Summary
The Fast Fourier Transform is an efficient algorithm for computing the discrete Fourier transform (DCT), and its speed is crucial in applications like signal processing, audio analysis, image processing, and many more where the frequency domain information of a signal is needed.
The FFT (Cooley, Tukey, 1965), an algorithmic technique, made the computation of the Fourier transform simpler and quicker and finally allowed Fourier analysis to be recognized and used more widely.
The key idea is to break down the computation into smaller DFTs recursively, taking advantage of the symmetry and periodicity properties.
The butterfly operation is a fundamental operation and a key element employed by FFT to efficiently compute the discrete Fourier transform (DFT).
A butterfly operation combines two points in the frequency domain, performing a specific computation involving addition and multiplication. The butterfly operation is called so because, when depicted graphically, the data flow diagram resembles the shape of a butterfly.
The most common version of FFT is the Radix-2 FFT, where the size of the input signal is a power of 2 (N = 2m).
The Cooley-Tukey Radix-2 FFT algorithm, one of the most commonly used FFT algorithms, employs the decimation-in-time (DIT) approach.
Typical time domain signals are, however, always real, i.e. the imaginary part is zero at every point in time. The imaginary part must be set to zero before the Fourier transform or its numerical variations FFT are performed.
The recursive application of these operations reduces the overall computational complexity of the FFT algorithms.
Compared to the direct DFT computation complexity of O(N2), the FFT, utilizing the Cooley-Tukey algorithm, achieves superior time complexity of O(N.log2 N), rendering it more suitable for larger input sizes due to its reduced computational demands.
If you have ever programmed an AVR microcontroller with a USB to serial adapter, you should know how it sometimes gets messy with all the data and power wires. Therefore, Adafruit created a UPDI programmer tool that can program newer tinyAVR and megaAVR chips with only 3 wires!
What is UPDI?
UPDI stands for Unified Program and Debug Interface. It is a Microchip proprietary interface and is a successor to the PDI interface, which has 2 data wires. UPDI provides a bidirectional half-duplex asynchronous communication with a microcontroller for programming or debugging. For more in-depth information about Microchip interfaces, you can find it here.
Where Adafruit get the inspiration?
SerialUPDI Programmer by Stefan Wagner was the inspiration. It had a long USB-A connector, 2.54 mm male pin headers for connections, a switch to choose 5V or 3.3V rail, and a CH340N USB-to-serial chip. It was a great proof-of-concept project and Adafruit made it even more user-friendly.
Is UPDI Friend better?
It is very small – 26.4 x 17.8 millimeters
Has a USB-C for data and power
There is a slide switch for selecting a 5V or 3V voltage rail. The 3V regulator can source up to 500mA of current
For programming, you can either solder wires to the 3 pads or use the included JST SH cable for poking into the breadboard
There are also two LEDs, green is for power OK and red for serial activity
Uses CH340E USB-to-serial chip
What chips you can program?
As mentioned earlier you can program newer tinyAVR and megaAVR microcontroller chips that have UPDI. Especially ATtiny boards like ATiny816, ATtiny817, or ATtiny1616. Adafruit recommends using Arduino IDE with the megaTinyCore board support package installed. For the programmer type, you need to select “Serial UPDI”. Upload speed of 230Kbps is great, but 56Kbps also works.
More information
You can get the UPDI Friend board from Adafruit for 6.95$, additional JST to socket headers cable will cost you 1.50$. There is also a how-to-use-it guide on the Adafruits overview page.
The original Simulation Program with Integrated Circuit Emphasis (SPICE) was introduced in 1973. Engineer Mike Engelhardt began developing his version of SPICE a quarter-century after its inception. Fast forward another 25 years and Qorvo has unveiled QSPICE, the company’s latest advancement in mixed-mode SPICE simulation.
“Basically, QSPICE is what I would have written 25 years ago when I wrote LTspice had I known then what I know now.” — Mike Engelhardt
In the real world, many circuits aren’t purely analog or digital. They’re a mix of both. For instance, imagine a power control chip: it might have analog components for managing voltage and current, but also digital parts for controlling the overall operation. These are mixed-mode circuits.
Now, traditional SPICE tools have often focused on either analog or digital circuits, not both. This can be a problem for companies like Qorvo, whose components are used in mixed-mode designs. Regular SPICE tools might not handle these mixed circuits well, leading to inaccurate simulations or poor performance.
That’s where QSPICE comes in. It’s specifically designed to handle mixed-mode circuits effectively. It’s like a more advanced version of SPICE that can accurately simulate both analog and digital parts of a circuit, ensuring better performance and reliability for engineers working with Qorvo’s components.
SMPS with a controller IC written in C++
QSPICE stands out due to its comprehensive support for mixed-mode simulations. A notable example is its capability to simulate Switched-Mode Power Supplies (SMPS) featuring a controller IC written in C++. This demonstrates QSPICE’s proficiency in integrating complex logic. Before the simulation, QSPICE compiles C++ and Verilog models into native code, resulting in simulations that run faster than the actual integrated circuits, according to Engelhardt. This tight integration also allows for the inclusion of significant amounts of digital logic within analog simulations.
In addition to its advancements in mixed-mode simulation, QSPICE underwent significant re-architecting of its analog analysis compared to Engelhardt’s previous work. The primary objective was to address singularities and discontinuities in IV curves. Moreover, the numerical methods inherited from the original Berkeley SPICE have been extensively updated to leverage modern PC architectures.
Despite being in Beta status, QSPICE boasts many features and tools. For instance, it includes a comprehensive plotting engine with cursor functionalities. Users familiar with Engelhardt’s previous simulator will find the schematic editor’s user experience instantly recognizable. However, new users are encouraged to watch a QSPICE quick-start video, as basic functionality may not be immediately apparent due to the absence of conventional menus or context clues typically found in modern software interfaces.
QSPICE, developed by Qorvo, includes models for Qorvo’s silicon carbide devices and advanced power management solutions. It also supports third-party models, allowing users to directly paste “.model” and “.subckt” models into the software. QSPICE’s schematic editor generates appropriate symbols automatically. It’s a fast, powerful simulation tool, particularly suited for mixed-mode designs like switch-mode power supplies. Available for Windows only, it’s free for commercial use but requires registration at QSPICE.com.
TensorFlow 2.15 simplifies using NVIDIA’s CUDA for AI on Linux with a single pip command and boosts performance with updates like CUDA 12.2 and Clang 17. It enhances machine learning efficiency on Windows and introduces advanced tf.function types for broad device compatibility.
Launched in 2017, TensorFlow is a free and open-source library developed by Google for machine learning and artificial intelligence applications. It supports applications ranging from high-performance computing to on-device machine learning with TensorFlow Lite for Microcontrollers. With all these features, the TensorFlow model is widely used for creating and training models to recognize patterns and make decisions based on data. Now with the new update, it allows Linux users to install NVIDIA CUDA libraries directly via pip with pip install tensorflow[and-cuda], eliminating the need for other CUDA packages if the NVIDIA driver is already installed.
A major update in TensorFlow 2.15 makes it much easier for Linux users to get started: now, you can set up TensorFlow and all necessary NVIDIA libraries to speed up AI tasks with just one command. As long as your computer already has NVIDIA drivers, TensorFlow should work faster and more efficiently.
New TensorFlow 2.15 Features:
Simpler Installation for NVIDIA CUDA Libraries on Linux:
Optional pip installation method for NVIDIA CUDA libraries through pip install tensorflow[and-cuda].
Only requires an NVIDIA driver on the system, no pre-existing NVIDIA CUDA packages are needed.
CUDA upgraded to version 12.2.
oneDNN CPU Performance Optimizations for Windows:
Enabled by default on x86 CPUs for Windows x64 & x86 packages.
Optimizations can be toggled with the TF_ENABLE_ONEDNN_OPTS environment variable.
Full Availability of tf.function Types:
tf.types.experimental.TraceType for Tensor decomposition and type casting in custom tf.function inputs.
tf.types.experimental.FunctionType as a comprehensive representation of tf.function callables’ signatures.
tf.types.experimental.AtomicFunction for the fastest way to perform TensorFlow computations in Python (gradient support not included).
Upgrade to Clang 17.0.1 and CUDA 12.2:
TensorFlow PIP packages are built with Clang 17 and CUDA 12.2 for enhanced performance, especially on NVIDIA Hopper-based GPUs.
Clang 17 is set as the default C++ compiler for TensorFlow builds.
Keras Updates:
Starting with Keras 3.0, release updates for the new multi-backend Keras will be published on keras.io.
Other features for TensorFlow 2.15 include a boost in performance with oneDNN on Windows, updates to CUDA 12.2 for better NVIDIA GPU efficiency, switches to Clang 17 as the standard compiler, and fully introduces tf.function types, including tf.types.experimental.AtomicFunction for faster Python computations.
The latest version of TensorFlow is accessible on GitHub, released under the flexible Apache 2.0 license.
On Kickstarter we just found out about this The Smallest Apple Watch Charger which can do a lot more than charge your Apple watch, it is a multi-functional wireless charging solution featuring 3.3W Qi-certified magnetic charging, PD3.1 compatibility through a 140W USB-C to C cable for fast device charging and data transfer. the device also has three additional USB-C ports for charging your other device.
The charger has advanced charging technology that ensures devices are powered up quickly and safely. It’s compatible with all series of Apple Watches and can also charge other devices such as smartphones, tablets, and laptops that support USB-C charging.
This charger is perfect for anyone who’s always on the move. Its small size means you can easily slip it into your pocket or bag, making it super handy for travel, work, or just at home. With this charger, Apple Watch users and anyone juggling multiple devices can breathe easily. No more lugging around different chargers or hunting for open ports—it’s got you covered for everything.
The device features a Micro-USB port and two USB-C ports. The device can also wirelessly charge all Apple watch series at up to 3.5W. The USB-C public port supports PD3.1 fast charging for devices with USB-C ports, including iPads. It includes a USB-C to B adapter for older laptops, offering a wide range of input/output options: 5V/2-3A, 9V/2A-4A, 12V/1.5A-6A, 20V/3-12A, with PD 3.0/2.0 and QC 4.0+/4.0/3.0/2.0 compatibility.
Multi-Function Apple Watch Charger Features:
Stylish 2-in-1 Device: Wireless magnetic charging for Apple watches, equipped with USB-Micro, USB-C, and a USB-C public port for various devices.
High Compatibility: Supports PD3.1 fast charging protocol; includes a USB-C to B adapter for older laptops.
Simultaneous Charging: Capable of charging three devices at once, including laptops, phones, and watches.
Advanced Safety Features: Qi-certified with intelligent temperature control, foreign object detection, and more for safe charging.
Efficient Design: Features an aluminum alloy heat sink shell for quick heat dissipation, improving battery life.
Magnetic Alignment: Ensures stable and efficient charging with accurate magnetic alignment.
Fast Data Transfer: Offers data transfer speeds of up to 480 Mbps with the 140w USB-C to C charging data cable.
Travel-Friendly: Compact and lightweight design with a round ring clasp for easy portability.
Unique Design: Distinguished by its unique polygonal design, suitable for charging Apple and Samsung watches.
Kickstarter offers early backers discounts on a 4-in-1 Apple Watch Charger with prices from $29 to $146. Deals vary from 50% to 60% off for 1 to 5 chargers, including USB-C and Qi-certified magnetic charging. The estimated delivery is from Feb to Apr 2024.
GigaDevice introduces the GD32W515 Development Board, an all-in-one development platform centered around the GD32W515PIQ6 Arm Cortex-M33 microcontroller. The board features integrated storage, sensors, and connectivity options, designed for comprehensive hardware and software evaluation.
The board features GigaDevice’s GD32W515PIQ6 microcontroller with an Arm Cortex-M33 core, 448kB of SRAM, 2MB of flash memory, and 43 GPIO pins, though these aren’t accessible for external use. It includes a GD25Q128E SPI NOR flash for an additional 16MB of storage, a built-in microphone, and a vibrator but lacks a speaker. It offers two expansion headers for a 0.96″ IPS LCD display and a GSL6157 sensor-based fingerprint scanner, plus a decorative capacitive switch styled as a fingerprint on the board.
The GD32W515 Development Board Specification:
MCU: GD32W515PIQ6 from GigaDevice, featuring an Arm Cortex-M33 core at up to 180 MHz with Arm TrustZone
Memory: 448KB SRAM
On-board Storage: 2MB flash
External Storage: 128Mbit SPI NOR Flash (GD25Q128E)
Connectivity: Wi-Fi 4 (802.11b/g/n) at 2.4 GHz (not utilized on the board)
I/O Capabilities: Up to 43 GPIOs, 3 USART, 2 I2C, 2 SPI, USB 2.0 Full Speed, I2S
Package: QFN56
Display Interface: 0.96-inch color IPS display with 160×80 resolution
Audio Features: Built-in microphone
Sensors:
GSL6157 capacitive fingerprint sensor
Temperature sensor
Programming/Debugging Tools:
GD-Link debugger (JTAG/SWD) using a mini USB port
Serial console over the micro USB port with CH340E serial chip
Miscellaneous: Vibrator, battery charging LEDs, 4 user LEDs, capacitive touch key linked to the MCU’s TSI interface
Power Supply Options:
5V via mini USB
LiPo battery connector with charging management (up to 1.5A) using GD30BC2416
Power selection switch for battery or USB
The GD32W515 evaluation kit fully utilizes its I/Os for built-in functions, ideal for smart home interfaces, door locks, and portable devices. It supports development with Arm Keil v5.29 IDE and firmware flashing via the “GD32AllInOneProgrammer” through GD-Link. Access to the user guide and project folder requires company approval, which may take a few days.
At the time of writing the company didn’t provide any price tag for this but you can get one for free by requesting one on the product page.
The Toybrick TB-RK3588SD is a single-board computer(SBC) powered by the Rockchip RK3588S, equipped with 8GB LPDDR4X RAM and a dual-core GPU and NPU for AI. It’s designed for multimedia applications in AI, VR, and cloud computing, all while maintaining a similar form factor to a Raspberry Pi.
The RK3588S SoC combines quad-core Cortex-A76 (up to 2.4GHz) and Cortex-A55 (up to 1.8GHz) CPUs, an ARM Mali-G610 MP4 GPU (up to 1GHz), and a 6-TOPS NPU. This configuration supports advanced graphics with OpenGL ES3.2, OpenCL 2.2, Vulkan 1.1, and high-performance 2D/3D acceleration. It also features video decoding up to 8K@60fps, encoding up to 8K@30fps, and is compatible with various AI frameworks, making it ideal for AI and multimedia applications.
The Toybrick TB-RK3588SD offers multiple video interfaces, including MIPI-DSI, HDMI, and DisplayPort via USB Type-C, supporting 8K@60fps decoding (H.265/VP9) and 8K@30fps encoding (H.265/H.264). Designed for applications in AI, cloud and edge computing, VR/AR, and gaming, further details are available on the Toybrick Wiki.
The Toybrick TB-RK3588SD is available in three packages: Basic Kit (board only), 20W PD PSU Kit (board + 20W PD power), and Development Kit (board, 20W PD power, 32GB MicroSD, MicroSD reader). The powerboard features include three buttons, LEDs, USB to serial, a six-axis sensor (three-axis accelerometer and gyroscope), power management, 2.5GHz/5.0GHz antennas, a 5V fan connector, and an SPI interface for TFT screens.
Toybrick TB-RK3588SD SBC Specification:
SoC:Rockchip RK3588S with quad-core Cortex-A76 and quad-core Cortex-A55, 8nm, up to 2.4GHz
The Toybrick TB-RK3588SD can be purchased from the Youyeetoo online store, with the 4GB version priced at $115 and the 8GB version at $128, both included in the basic package.
Waveshare has launched two new ESP32-S3 modules: the ESP32-S3-SIM7670G-4G and the ESP32-S3-A7670E-4G. Both support 4G, GNSS, Wi-Fi, Bluetooth, and solar charging, and have a holder to put in an 18650 battery. The main difference is in their cell network support. The SIM7670G model works with a wide range of 4G networks while The A7670E model supports both 4G and 2G networks.
Previously, we’ve explored several LTE-based modules, including the SparkFun LTE Stick, Project Walter, and PicoCell 4G If you’re interested in this topic, feel free to check out those discussions for more insights.
The ESP32-S3-A7670E-4G board is powered by the ESP32-S3R2 chip with a dual-core processor at 240MHz, 512KB SRAM, 384KB ROM, 2MB PSRAM, and 16MB Flash, and supports 4G and 2G networking, along with GNSS positioning capabilities for GPS, BeiDou, and GLONASS, facilitated by a GNSS IPEX1 connector.
The board also includes an OV2640 camera (1600×1200 resolution, 15fps), microphone and speaker for calls, USB Type-C, MicroSD slot, RGB LED, and DIP switches for controlling the camera, USB, and 4G module.
The board has a built-in IC for charging lithium batteries, managing power, and measuring battery capacity. It also includes safety circuits and supports both USB and solar charging, with the ability to measure battery capacity in real-time.
Nordic Semiconductor has recently unveiled nRF54L15 a Cortex-M33 multi-protocol wireless microcontroller targeting a wide range of IoT applications such as smart home, industrial IoT, and medical devices. This series combines improved processing power, energy efficiency, and advanced security features for advanced IoT applications.
The nRF54L15 targets a wide array of wireless IoT applications, including PC peripherals, gaming, remote controllers, VR/AR devices, Smart Home gadgets with Matter compatibility, healthcare monitors, and industrial tools. Nordic Semiconductor announces the availability of the nRF54L15 for initial testing in a QFN48 package, featuring 31 GPIOs. Additionally, the firm is set to introduce two significantly smaller WLCSP packages, offering a footprint reduction of over 50% compared to the nRF52840, designed for space-sensitive projects. These packages will provide 32 GPIOs at a 0.3mm pitch and 14 GPIOs at a 0.35mm pitch.
Nordic Semiconductor nRF54L key features and specifications:
CPU: Arm Cortex-M33, up to 128 MHz; includes up to 1.5 MB Flash and 256 KB SRAM, plus a RISC-V coprocessor for enhanced flexibility.
Wireless Capabilities:
Bluetooth 5.4 LE: Supports direction-finding, and Bluetooth mesh, and is prepared for future Bluetooth updates.
802.15.4 Radio: Enables Thread and Matter connectivity.
Proprietary 2.4 GHz Communication: Allows speeds up to 4 Mbps.
High Sensitivity and Power: -96 dBm RX sensitivity at 1 Mbps for Bluetooth LE, with up to 8 dBm TX power.
New Peripherals: Includes a Global RTC, 14-bit ADC, and software-defined peripherals for expanded functionality.
Security: Built for PSA Certified Level 3, featuring TrustZone isolation, side-channel protection, and tamper detection for top-tier IoT security.
Power Efficiency: RX current consumption is half that of its predecessor, the nRF52840, for improved battery life.
Package Options: Available in QFN48 (6×6 mm) and ultra-compact WLCSP (2.4×2.2 mm) formats to suit various design needs.
Manufacturing Process: Utilizes TSMC’s advanced 22ULL (22 nm) process technology for enhanced performance and efficiency.
At the time of writing the full details and specifications for Nordic Semiconductor nRF54L are yet to be shared publicly. For more information, interested individuals should contact their local Nordic sales representative. Eventually, everything required to begin will be accessible on the product webpage, and the press release might offer some additional details.